Semiconductor wafers are used in the production of semiconductor devices such as integrated circuit (IC) chips, silicon-on-insulator (SOI) wafers, and radio frequency-SOI (RF-SOI) wafers. Typically, the semiconductor wafers used for RF-SOI include a high resistivity substrate that can be susceptible to formation of a high conductivity inversion or accumulation layer. This inversion or accumulation layer hinders the performance of the semiconductor devices.
In some processes, a layer, such as a polycrystalline silicon layer, is deposited onto a surface of the semiconductor wafer to provide a density charge trap and, thereby, inhibit the formation of the high conductivity inversion or accumulation layer. For example, the layer can be deposited onto a surface that forms the interface between the high resistivity substrate and a buried oxide (BOX) to hinder the movement of charges across the interface.
The effectiveness of charge trapping in semiconductor structures depends on multiple factors including the density of crystal defects, polysilicon structure (grain size), polysilicon deposition [CVD] conditions, status of the polysilicon to silicon substrate interface, doping level, resistivity, interface states, surface contamination and thermal treatment applied during device manufacturing. To ensure a proper charge trapping efficiency, a great variety of technological parameters are carefully controlled and monitored during manufacturing of charge-trapping layer semiconductor wafers for RF device applications. A measurement of charge trapping efficiency is an important component in quality control in charge-trapping layer semiconductor structure manufacturing.
Conventional methods of measuring charge trapping efficiency in semiconductor wafers are based on testing radiofrequency (RF) device performance. RF devices are built on top of the wafers and then tested. The process of RF device manufacturing involves many technological steps and is time consuming. Feedback on the quality of the wafer processing is delayed and this may incur significant throughput and yield losses in wafer manufacturing.
A continuing need exists for methods for assessing the quality of a semiconductor structure such as for use in radiofrequency devices and, in particular, methods that are relatively quick, non-destructive and do not require RF device fabrication.
This section is intended to introduce the reader to various aspects of art that may be related to various aspects of the disclosure, which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present disclosure. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.